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Class Presentation For Advanced VLSI Course

Professor: Dr. S. M. Fakhraie

Presented by: Sayyed Hassan Sohofi

Major Reference: A 0.13µm Triple-Vt 9MB Third Level On-Die

Cache for the Itanium® 2 ProcessorBy:

Jonathan Chang, Jonathan Shoemaker, Mizan Haque, Ming Huang,Kevin Truong, Mesbah Karim, Siufu Chiu, Gloria Leong, Kiran Desai,

Richard Goe, Sandhya Kulkarni, Arun Rao, Daniel Hannoun, Stefan RusuIntel Corporation, Santa Clara, CA

In:2004 IEEE International Solid-State Circuits Conference

Winter 2004

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Outline Processor highlights Itanium® processor evolution Itanium®2 Architecture Cache Hierarchy L3 cache trends 9MB cache organization Stage mode ECC logic Frequency shmoo Summary References

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Itanium® 2 Processor 9M Highlights 592M transistor 432mm2 die size 9MB on-die L3 cache 1.7GHz at 1.35V 6.4GB/s 400MT/s 4-way

bus interface Read and write

bandwidth 54 GB/s EPIC Architecture 4-port cache memory For Technical and

Commercial Servers

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Itanium® Processor Evolution

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Itanium®2 Architecture

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Itanium®2 Architecture

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Cache Concepts Terminology

● Hit: data appears in some block in the upper level

● Miss: data needs to be retrieve from a block in the lower level

Block placement● Direct map● Fully Associative● Set Associative

Block replacement● Random● FIFO● LRU● NRU● LFU

Write strategy● Write through● Write back

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Set Associative Mapped Cache

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Cache Hierarchy

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Cache Hierarchy

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Hit Detection

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L3 Cache Trends

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L3 Subarray

Subarray Size: 2 * 8 * (96*256) = 48 KB

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Cache Organization

96*256

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Group Extension for 9M

Data-group

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Stage Mode Logic

Maintain 4-cycle tag look-up when no ECC error occurs Re-circulate the request and perform in-line ECC error correction when

detecting an ECC error with one additional cycle Can permanently set tag look-up to 5-cycle if desired Special logic handling and mutually-exclusive guarantee circuitry added

for false hit and dummy read

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Stage Mode Logic

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L3 Behavior with ECC Errors

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L3 Behavior with ECC Errors

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L3 Behavior with ECC Errors

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L3 Behavior with ECC Errors

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L3 Behavior with ECC Errors

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Infrared Emission Photo

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Frequency Shmoo

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Summary Itanium® is a processor for technical and commercial

servers applications Itanium® 2 Processor 9M has the largest on-die cache and

transistor count reported for a processor Modular cache extension methodology enables reuse of

existing subarray and floorplan Three-Level cache for satisfying technical and commercial

applications 50 bit of physical address to provide 1024 Tbyte of

addressability Stage mode ECC logic maintains existing latency and adds

one extra cycle only for ECC correction events Best performance at 1.7GHz and 1.35V

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References[1] Jonathan Chang, Jonathan Shoemaker, Mizan Haque, Ming Huang, Kevin Truong, Mesbah Karim, Siufu Chiu, Gloria

Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni, Arun Rao, Daniel Hannoun, Stefan Rusu, “A 0.13µm Triple-Vt 9MB Third Level On-Die Cache for the Itanium® 2 Processor” ISSCC 2004 Conference

[2] Cameron McNairy,Don Soltis ”ITANIUM 2 PROCESSOR MICROARCHITECTURE” IEEE Computer Society MARCH–APRIL 2003 PP 44-55

[3] John Hennessy, David A. Patterson “Computer Architecture: A Quantitative Approach” 2003 Edition

[4] Stefan Rusu, Harry Muljono, Brian Cherkauer “ITANIUM 2 PROCESSOR 6M: HIGHER FREQUENCY AND LARGER L3 CACHE” Computer Society MARCH–APRIL 2004 PP 10-18

[5] J. Stinson, S. Rusu, “A 1.5GHz Third Generation Itanium® Processor” ISSCC Dig. Tech. Papers, pp 252-253, Feb. 2003.