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adaptive body bias for reducing process variations

nuno alves

19 / october / 2006

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background

goal of processor design:

• achieve maximum operating frequency

• meet power density constraint

process variations create differences:

• across a single die

• across multiple wafers and lots

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differences in transistors ? so?

some dies cannot be accepted because:

• low frequency

• high power consumption

dies

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solving leakage problem…

leakage can be controlled to some extent using body bias.

remember: non-zero body-to-source bias can modulate the threshold voltage of a transistors

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reverse body bias (rbb)

we can use rbb to reduce leakage power in standby mode by:

• raising the voltage of the pMOS n-wells with respect to vdd

or

• lowering the voltage of substrate relative to gnd

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forward body bias (fbb)

Vt by the lowering the source-body potential barrier

lower Vt = higher on current

hence higher performance

the good

the bad

increase in sub-threshold and substrate-to-source leakage

slows down the discharge of nodes

use fbb to increase operating frequency in active mode

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ideally

Vt should be

• lowered for slow dies• raised for leaky dies

accomplished by an adaptive body bias

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testchip

21 subsites

each subsite contains:• an abb generator• control circuit

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how it works? pt 1

the desired operating frequency is applied externally

slows things down

compare critical path with target clock period

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how it works? pt 2 output of first ff is sampled by second ff

this allows sufficient time for the body bias to stabilize

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how it works? pt 3

PD used to clock a counter

counter whose value represents the body bias to apply

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how it works? pt 4

converting digital codeto an analogical bodyvoltage

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how it works? pt 5

the output voltage, which biases the the pMOS transistors is a function of

• VREF

• VCCA

output voltage

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how it works? pt 6

setting the bias by modifying:

• VREF

• VCCA

and

• setting a counter control bit

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operation pt 1

initially frequency is lower than the target one

body voltage reduces, forward biasing the pMOS transistor & increasing frequency

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operation pt 2

phase detector changes to a permanent 1

frequency has been matched

the counter is disabled, maintaining the body voltage

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operation pt 3

once optimal voltages are determined, they can be programmed in the chip or supplies externally

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simple adaptive body bias pt 1

optimum bias voltages are determined through measurements

example:

1. a microprocessor with many circuit blocks.

2. find out the frequency of a critical path

3. a central body bias determines the body bias to apply to achieve a desired frequency.

4. apply this bias everywhere

2% total die area overhead

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simple adaptive body bias pt 2

optimum bias is determined by applying a target clock frequency…

…highest possible operating frequency for the die under the given power constraint.

maximum clock frequency

for this maximum frequency

• nMOS body bias is applied from outside

• pMOS body bias comes from on-chip control circuitry

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simple adaptive body bias pt 3

repeat until we find the best combination of lowest leakage with target frequency

pick target frequency

manually adjust nMOS body bias

pMOS body bias automatically adjusts

determine leakage power

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effects of simple body bias pt1NBB = no body bias

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effects of simple body bias pt2

• when no body bias, only 50% dies are acceptable

conclusion 1:

… mostly in the low frequency bin

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effects of simple body bias pt3

• frequency variation was reduced to 1% from 4.1%

• more accepted dies (specially in the high frequency range)

conclusion 2:

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effects of simple body bias pt4

conclusion 3:

many dies fail to meet the leakage constraint…

… due to the fact that a single circuit block is used to determine the body bias for all circuit…

… and there are always intra-die variations.