Post on 25-Apr-2020
Microprocessors80x86 Family Overview1
Dr. Martin LandHadassah CollegeSpring 2011
Intel x86Memory
Architecture
Microprocessors80x86 Family Overview2
Dr. Martin LandHadassah CollegeSpring 2011
“The x86 isn't all that complex — it just doesn't make a lot of sense.”
Mike Johnson, Leader of 80x86 Design at AMD, Microprocessor Report (1994)
Microprocessors80x86 Family Overview3
Dr. Martin LandHadassah CollegeSpring 2011
Program SegmentsData and BSS sections
ConstantsInitialized and uninitialized variablesTables, arrays, stringsStructures
Text sectionProcedures / functions / control blocksData access
Load operations — RAM to registerStore operations — register to RAMPeripheral I/O operations
CalculationArithmetic operations Logic operations
Stack sectionLIFO buffer accessible by PUSH / POP operations
Microprocessors80x86 Family Overview4
Dr. Martin LandHadassah CollegeSpring 2011
x86 Data and Address Ranges
data
physical addressx86 RAM
00000000 to FFFFFFFF4 GB
00000 to FFFFF1 MB
Physical Memory
3220Address bits
–2G to +2G - 1–32K to 32K – 1Signed Integer
0 to 4G0 to 64KUnsigned Integer
3216Data bits
Windows/LinuxDOS
K = 210 = 1024 M = 220 = 10242G = 230 = 10243
Microprocessors80x86 Family Overview5
Dr. Martin LandHadassah CollegeSpring 2011
Logical Address CPUx86 access to physical RAM
CPU accesses external deviceAccess by physical address
20 bits (8086) or 32 bits (IA-32)
Programs do not see physical addressSoftware address = logical address = SEG:OFFSEG
Segment selector in CPU segment registerMaps to Physical Base AddressPointer to start of segment in memory
OFFOffset formed by pointer arithmeticPointer to byte in segment
Physical Address = Physical Base Address + Offset
PhysicalBase
Address
Offset
PhysicalAddress
RAM
data
addressx86 RAM
Microprocessors80x86 Family Overview6
Dr. Martin LandHadassah CollegeSpring 2011
x86 Segment Registersx86 segments are sections of physical memory
No one-to-one connection with program segments
Six defined memory pointers
DS (name ~ Data Segment)CS (name ~ Code Segment)SS (name ~ Stack Segment)ES (name ~ Extra Segment)FS, GS ⎯ in IA-32 only
Six segment registers
GS selector GS FS selector FS ES selector ES SS selector SS CS selector CS DS selector DS
15 0
ES
RAM
SS
CS
DS
FS
GS
Microprocessors80x86 Family Overview7
Dr. Martin LandHadassah CollegeSpring 2011
Typical Segment Register Usage
ES
DS
CS
SS
DS = ES = CS = SS
DS = ES = CS = SS= FS= GS
DOS *.com programOne 64 KB segment
DOS *.exe programFour defined segmentsSegment ≤ 64 KB
Linux softwareOne 4 GB segmentOS allocates memory
to programs
Microprocessors80x86 Family Overview8
Dr. Martin LandHadassah CollegeSpring 2011
Mapping Segment8086 segment mapping
SEG = 16-bit segment SELECTOR in segment registerSEG × 10h = 20-bit physical base address
segment register const
0SEG = segment selector 4 bits16 bits
IA-32 segment mappingSEG = 16-bit segment SELECTOR in segment register
Selector is index to descriptor tableDescriptor is table entry holding
32-bit or 64-bit physical base addressSegment sizeSegment typeSegment access rights descriptor
descriptor
descriptor
descriptor
descriptor
descriptor
selector
physical base address
Microprocessors80x86 Family Overview9
Dr. Martin LandHadassah CollegeSpring 2011
8086 Segments RegistersFour segment registers
Extra ES Stack SS Code CS Data DS
15 0
DS × 10h
RAM
CS × 10h
SS × 10h
ES × 10h
20-bit segmentbase addresses
segment register const
0SEG = segment selector 4 bits16 bits
Microprocessors80x86 Family Overview10
Dr. Martin LandHadassah CollegeSpring 2011
8086 Segment Example16-bit segment registers
4000 ES 3000 SS 2000 CS 1000 DS
15 0
extra
10000
RAM
stack
code
data
20000
30000
40000
20-bit segmentbase addresses
40000 Extra 30000 Stack 20000 Code 10000 Data
20-bit physical base address
Microprocessors80x86 Family Overview11
Dr. Martin LandHadassah CollegeSpring 2011
8086 OffsetOffset
16-bit numberCombination of registers and immediate values Offset ∈ {0000, 0001, 0002, … , FFFF}
216 possible offset values Maximum segment = 216 bytes = 64 KB
Physical Address = physical base address + offset
ExampleLogical Address = 1234:0005Segment selector = 1234Physical base address = 12340Physical Address = 12340 + 0005 = 12345
PhysicalBase
Address
Offset
PhysicalAddress
RAM
Byte
byte
byte
byte
byte FFFF
0000
0001
0002
…
Microprocessors80x86 Family Overview12
Dr. Martin LandHadassah CollegeSpring 2011
IA-32 OffsetOffset
32-bit numberCombination of registers and immediate values Offset ∈ {00000000, … , FFFFFFFF}
232 possible offset values Maximum segment = 232 bytes = 4 GB
Physical Address = physical base address + offset
ExampleLogical Address = 1234:11223344Segment selector = 1234Physical base address = 00000000Physical Address = 0 + 11223344 = 11223344
PhysicalBase
Address
Offset
PhysicalAddress
RAM
Byte
byte
byte
byte
byte FFFFFFFF
00000000
00000001
00000002
…
descriptor table
Microprocessors80x86 Family Overview13
Dr. Martin LandHadassah CollegeSpring 2011
Logical to Physical — Many to One Mapping8086 Physical Address
PA = 12345
Logical addressPA = SEG × 10h + OFFSEG = PA / 10h = 12345 / 10h = 1234
OFF = PA % 10h = 12345 % 10h = 0005
Equivalent logical addresses for PA = 123451234:0005 = 12340 + 00051233:0015 = 12330 + 00151232:0025 = 12320 + 0025
...
SEG:OFF → (SEG – n):(OFF + 10h × n)for integer 0 < n ≤ SEG and OFF + 10h × n < 10000h
PA → (SEG – n) × 10h + (OFF + 10h × n)= SEG × 10h + OFF = PA
PhysicalBase
Address
Offset
PhysicalAddress
RAM
Microprocessors80x86 Family Overview14
Dr. Martin LandHadassah CollegeSpring 2011
Program Segments versus Memory SegmentsSegment
Segment = any section, part, portion, subdivisionSegment ≠ specific, 1-to-1 technical meaning
Program segments (sections)Sections of assembly source code or executable programData segment
Space allocated for storing program data
Text (code) segmentSpace allocated for program instructions
Stack segmentSpace allocated for user stack operations
x86 memory segmentsDS, CS, SS, ES, FS, GS
Pointers to sections of physical memory (RAM)No one-to-one connection to program segments
Microprocessors80x86 Family Overview15
Dr. Martin LandHadassah CollegeSpring 2011
DOS Program Updates to Segments RegistersPrograms can write to segment registersExample
256 KB = 4 × 64 KB of data = 40000h bytesData occupies physical addresses 10000 to 4FFFFTo access all data, program must update DS:
DS ← 1000Access 10000, 10001, … , 1FFFF
DS ← 2000Access 20000, 20001, … , 2FFFF
DS ← 3000Access 30000, 30001, … , 3FFFF
DS ← 4000Access 40000, 40001, … , 4FFFF
40000
RAM
CS
SS
ES
30000
20000
10000
ProgramData
Section
Microprocessors80x86 Family Overview16
Dr. Martin LandHadassah CollegeSpring 2011
8086 Addressing Modes for Data
String Automatic Stack Automatic
AX ← DX Register
REGS[AX] ← REGS[DX] AX ← 1000 h
Immediate REGS[AX] ← #1000 h
AX ← [BX] Register Indirect
REGS[AX] ← MEM[DS*10 + REGS[BX]] AX ← [1000]
Absolute (Direct) REGS[AX] ← MEM[DS*10 + 1000]
AX ← [SI + 6] Indexed (SI or DI) REGS[AX] ← MEM[DS*10 + REGS[SI] + 6]
AX ← [BX + 6] Based (BX or BP) REGS[AX] ← MEM[DS*10 + REGS[BX] + 6]
AX ← [BX + SI] Based and Indexed
REGS[AX] ← MEM[DS*10 + REGS[BX] + REGS[SI]] AX ← [BX + SI + 6] Based and Indexed
with Displacement REGS[AX] ← MEM[DS*10 + REGS[BX] + REGS[SI] + 6]
Microprocessors80x86 Family Overview17
Dr. Martin LandHadassah CollegeSpring 2011
8086 Register Addressing ModeAddressing
Mode Example
Instruction Meaning
ADD BX,AX REGS[BX] ← REGS[BX] + REGS[AX] Register
Used for operands that the ALU is using now
SI DI BP AX BX CX DX SP1025 1004 0003 0031 0096 D400 9008 0000
0031
0096
00C7
Registers
Microprocessors80x86 Family Overview18
Dr. Martin LandHadassah CollegeSpring 2011
8086 Immediate Addressing ModeAddressing
Mode Example
Instruction Meaning
ADD BX,3 REGS[BX] ← REGS[BX] + 3 Immediate
Used for constant operands
SI DI BP AX BX CX DX SP1025 1004 0003 0031 0096 D400 9008 0000
0003
0096
0099
Registers
Microprocessors80x86 Family Overview19
Dr. Martin LandHadassah CollegeSpring 2011
8086 Absolute Addressing ModeAddressing
Mode Example
Instruction Meaning
ADD AL,[1001] REGS[AL] ← REGS[AL] + MEM[DS*10 + 1001] Direct Or Absolute Used for storing general data in main memory
SI DI BP AX BX CX DX SP1025 1004 0003 0031 0096 D400 9008 0000
29
31
5A
1007 001006 581005 001004 FF1003 9E1002 101001 291000 45
Registers
Main Memory(RAM)
Microprocessors80x86 Family Overview20
Dr. Martin LandHadassah CollegeSpring 2011
8086 Absolute Addressing ModeAddressing
Mode Example
Instruction Meaning
ADD DI,[1001] REGS[DI] ← REGS[DI] + MEM[DS*10 + 1001] Direct Or Absolute Used for storing general data in main memory
SI DI BP AX BX CX DX SP1025 1004 0003 0031 0096 D400 9008 0000
1029
1004
202D
1007 001006 581005 001004 FF1003 9E1002 101001 291000 45
Registers
Main Memory(RAM)
Microprocessors80x86 Family Overview21
Dr. Martin LandHadassah CollegeSpring 2011
8086 Indexed Addressing ModeAddressing
Mode Example
Instruction Meaning
ADD BX,[DI] REGS[BX] ← REGS[BX] + MEM[DS*10 + REGS[DI]] Register Deferred A pointer to data is kept in the register
SI DI BP AX BX CX DX SP1025 1004 0003 0031 0096 D400 9008 0000
00FF
0096
0195
1007 001006 581005 001004 FF1003 9E1002 A81001 291000 45
Registers
Main Memory(RAM)
Microprocessors80x86 Family Overview22
Dr. Martin LandHadassah CollegeSpring 2011
8086 Based Addressing ModeAddressing
Mode Example
Instruction Meaning
ADD BX,[BP] REGS[BX] ← REGS[BX] + MEM[SS*10 + REGS[BP]] Register Deferred A pointer to data is kept in the register
SI DI BP AX BX CX DX SP1025 1004 0003 0031 0096 D400 9008 0000
00FF
0096
0195
0007 120006 630005 240004 000003 FF0002 230001 350000 34
Registers
Main Memory(RAM)
BP forces access to SS
Microprocessors80x86 Family Overview23
Dr. Martin LandHadassah CollegeSpring 2011
8086 Index with Displacement Addressing ModeAddressing
Mode Example Instruction Meaning
ADD BX,[DI+2] REGS[BX] ← REGS[BX] + MEM[DS*10 + REGS[DI] + 2] Displacement
A constant offset is added to the pointer
SI DI BP AX BX CX DX SP1025 1004 0003 0031 0096 D400 9008 0000
0058
0096
00EE
1007 001006 581005 001004 FF1003 9E1002 A81001 291000 45
+2
Registers
Main Memory(RAM)
Microprocessors80x86 Family Overview24
Dr. Martin LandHadassah CollegeSpring 2011
8086 Based and Indexed Addressing ModeAddressing
Mode Example
Instruction Meaning
ADD BL,[DI+BP] REGS[BL]← REGS[BL]+ MEM[SS*10 + REGS[DI] + REGS[BP]] Indexed
A stored offset or table index is added to the pointer
SI DI BP AX BX CX DX SP1025 1004 0003 0031 0096 D400 9008 0000
00
96
96
1007 001006 231005 451004 341003 911002 381001 241000 35
+
Registers
Main Memory(RAM)
BP forces access to SS
Microprocessors80x86 Family Overview25
Dr. Martin LandHadassah CollegeSpring 2011
8086 Effective Address for Data Access
SEG OFF DS 16-bit Displacement DS BX BX + Displacement SS BP BP + Displacement DS SI SI + Displacement DS DI DI + Displacement DS BX + SI BX + SI + Displacement DS BX + DI BX + DI + Displacement SS BP + SI BP + SI + Displacement SS BP + DI BP + DI + Displacement
Effective Address (EA)OFFSET part of logical address for memory read/write Formed from immediate and register values
Microprocessors80x86 Family Overview26
Dr. Martin LandHadassah CollegeSpring 2011
Summary of 8086 Address TypesAddresses for General Data Access
BP SI Effective Address (EA) BX + DI + Displacement
Default Physical Address = DS×10h + Effective Address
EA includes BP ⇒ physical address = SS × 10h + EA
Instruction can override DS or SS to CS, ES, SS
Automatic Addresses (determined by operation)
Memory Access Logical Address Physical Address Instruction Fetch CS:IP CS×10h+IP Stack Operation SS:SP SS×10h+SP String Destination ES:DI ES×10h+DI String Source DS:SI DS×10h+SI
Microprocessors80x86 Family Overview27
Dr. Martin LandHadassah CollegeSpring 2011
8086 Segmentation Example: Instruction Fetch
Code SegmentAddress = 10000 h
Offset = 0057 Code Segment
Code Byte
Physical ByteAddress = 10057 h
RAM
Limit = 1FFFF h
Instruction Fetch -- Logical Address = CS:IPCS = 1000 -- Code Segment Physical Base Address = 10000 hIP = 0057Logical Address = CS:IP = 1000:0057
Microprocessors80x86 Family Overview28
Dr. Martin LandHadassah CollegeSpring 2011
8086 Segmentation Example: MOV AX,[BX]
Data SegmentAddress = 21000 h
Offset = 0123 Data Segment
Data Byte
Physical ByteAddress = 21123 h
RAM
Limit = 30FFF h
MOV Instruction -- DSEffective Address = BXLogical Address = DS:BX = 2100:0123
Microprocessors80x86 Family Overview29
Dr. Martin LandHadassah CollegeSpring 2011
8086 Segmentation Example: MOV AX,[BX+SI+7]
Data SegmentAddress = 21000 h
Offset = 112A Data Segment
Data Byte
Physical ByteAddress = 2212A h
RAM
Limit = 30FFF h
MOV Instruction -- DSEffective Address = BX+SI+7Logical Address = DS:BX+SI+7 = 2100:0123 + 1000 + 7
= 2100:112A
Microprocessors80x86 Family Overview30
Dr. Martin LandHadassah CollegeSpring 2011
8086 Segmentation Example: MOV AX,[BP+SI+2]
Stack SegmentAddress = 41000 h
Offset = 1242 Stack Segment
Stack Byte
Physical ByteAddress = 42242 h
RAM
Limit = 50FFF h
MOV Instruction with BP -- SSEffective Address = BP+SI+2Logical Address = SS:BP+SI+2 = 4100:0240 + 1000 + 2
= 4100:1242
Microprocessors80x86 Family Overview31
Dr. Martin LandHadassah CollegeSpring 2011
80186 Implementation
AddressBus
Control(MAR)
Decoderand
Control
StatusWord
ALU
Main Memory
GeneralRegisters
ExecutionUnit(EU)
BusInterface
Unit(BIU)IP
CSDS
SSES
AH ALBH BLCH CLDH DL
BP
SPSIDI
InstructionPointer
andSegmentRegisters
123456
InstructionQueue
System Bus
DataBus
Control(MDR)
ALU
ALU_IN
ALU_OUT
OFF
SEG
PA
PhysicalAddress
Data
20 bits 16 bits
Control
Decoder
AXBXCX
DX
PhysicalAddress
Unit(PAU)
BASEINDEXDISP
PA = 10 × SEG + BASE + INDEX + DISP
Microprocessors80x86 Family Overview32
Dr. Martin LandHadassah CollegeSpring 2011
Typical 8086 Instruction ImplementationInstruction Fetch
SEG ← CS ; OFF ← IP ; MAR ← PAIP ← IP + instruction lengthREAD
Instruction Queue ← MDRDecoder ← Instruction Queue
Instruction: ADD AL, [BX+SI+1234]SEG ← DS ; OFF(BASE) ← BXOFF(INDEX) ← SIOFF(DISP) ← 1234MAR ← PAREAD
ALU_IN ← MDRALU ← ALADD
AL ← ALU_OUT
Microprocessors80x86 Family Overview33
Dr. Martin LandHadassah CollegeSpring 2011
MOV in 8086
←
←⎯⎯⎯⎯⎯
←⎯⎯⎯⎯⎯
←⎯⎯⎯⎯⎯
←⎯⎯⎯⎯⎯
dest, src dest src
AX, [1234] REGS[AX] MEM[DS*10 + 1234]16-bits
REGS[AL] MEM[DS*10 + 1234] 8-bits
REGS[AH] MEM[DS*10 + 1235] 8-bits
AL, [1234] REGS[AL] MEM[DS 8-bit
MOV
MOV
sMOV
←⎯⎯⎯⎯⎯
←⎯⎯⎯⎯⎯
←⎯⎯⎯⎯⎯
*10 + 1234]
AX, [BX] REGS[AX] MEM[DS*10 + REGS[BX] ]16-bits
AX, [BX+SI] REGS[AX] MEM[DS*10 + REGS[BX] + REGS[SI] ]16-bits
AX, [BX+
MOV
MOV
M SI+12] REGS[AX] MEM[DS*10 + OV REGS[BX]16-bits
+ REGS[SI] + 12]
Microprocessors80x86 Family Overview34
Dr. Martin LandHadassah CollegeSpring 2011
8086 Stack Operations
PUSH src
POP dest
[ ]←
←⎯⎯⎯⎯16-bits
SP SP - 2
SS:SP src
[ ]←⎯⎯⎯⎯
←16-bitsdest SS:SP
SP SP + 2
Microprocessors80x86 Family Overview35
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8086 Segment Override
CS: MOV [BP],CX [CS:BP] ← CX ES: MOV [BP],CX [ES:BP] ← CX DS: MOV [BP],CX [DS:BP] ← CX SS: MOV [SI],CX [SS:SI] ← CX
Microprocessors80x86 Family Overview36
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8086 String Instructions ⎯ 1
[ES:DI] ← AL DI ← DI+1 (default) STOSB
Store String Byte (DI ← DI-1 if flag DF = 1)
[ES:DI] ← AL [ES:DI+1] ← AH DI ← DI+2 (default)
STOSW Store String Word
(DI ← DI-2 if flag DF = 1) AL ← [DS:SI] SI ← SI+1 (default) LODSB
Load String Byte (SI ← SI-1 if flag DF = 1)
AL ← [DS:SI] AH ← [DS:SI+1] LODSW
Load String Word SI ← SI+2 (default)
(SI ← SI-2 if flag DF = 1)
Addresses defined by instruction
Microprocessors80x86 Family Overview37
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8086 String Instructions ⎯ 2
MOVSB Move
String Byte
[ES:DI] ← [DS:SI] DI ← DI+1 (default) SI ← SI+1 (DI ← DI-1 if DF = 1) (SI ← SI-1 if DF = 1)
MOVSW Move
String Word
[ES:DI] ← [DS:SI] [ES:DI+1] ← [DS:SI+1] DI ← DI+2 (default) SI ← SI+2 (DI ← DI-2 if DF = 1) (SI ← SI-2 if DF = 1)
SCASB Scan
String Byte
AL-[ES:DI]; update flags DI ← DI+1 (default) (DI ← DI-1 if DF = 1)
Microprocessors80x86 Family Overview38
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8086 String Instructions ⎯ 3
SCASW Scan
String Word
AX-[ES:DI+l.DI]; Update flags DI ← DI+2 (default) (DI ← DI-2 if DF = 1)
CMPSB Compare String Byte
[DS:SI]-[ES:DI]; Update flags DI ← DI+1 (default) SI ← SI+1 (DI ← DI-1 if DF = 1) (SI ← SI-1 if DF = 1)
CMPSW Compare String Word
[DS:SI+1.SI]-[ES:DI+1.DI]; Update flags DI ← DI+2 (default) SI ← SI+2 (DI ← DI-2 if DF = 1) (SI ← SI-2 if DF = 1)
Microprocessors80x86 Family Overview39
Dr. Martin LandHadassah CollegeSpring 2011
8086 String Instructions ⎯ 4
REP STOSB STOSB CX ← CX - 1 Repeat until CX = 0
REP STOSW STOSW CX ←CX - 1 Repeat until CX = 0
REP MOVSB MOVSB CX ← CX - 1 Repeat until CX = 0
REP MOVSW MOVSW CX ← CX - 1 Repeat until CX = 0
Microprocessors80x86 Family Overview40
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Working with Strings
PUSH ES ; SP ← SP – 2; [SS:SP] ← ES
PUSH DS ; SP ← SP – 2; [SS:SP] ← DS
POP ES ; ES ← DS; SP ← SP + 2
MOV SI,0000 ; SI ← 0MOV DI,1000 ; DI ← 1000MOV CX,200 ; CX ← 200REP MOVSB ; COPY 200 H BYTES FROM
; DS:0000 – DS:01FF TO ; DS:1000 – DS:11FF
Microprocessors80x86 Family Overview41
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Branch Instructions
Fall-throughInstruction following branch in program listingNext instruction if branch not takenCS:IP points to fall-through
TargetNext instruction if branch takenCS:IP points to target
DisplacementDisplacement = target IP – fall-through IP
Displacement > 0 is forward jumpDisplacement < 0 is backward jump
branch
target
fall through
branchtaken
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Jump DistanceDisplacement
target IP – fall-through IP
Short JumpTarget in same code segment Displacement is byte
Near JumpTarget in same code segment Displacement is word (2 bytes)
Far JumpTarget in different code segmentPointer is double word (4 bytes)Displacement not relevant
branch
short target
near target
far target
shortjump
nearjump
farjump
fall through
≤ ≤10 10-128 = 80 displacement 7F = 127
≤ ≤10 10-32,768 = 8000 displacement 7FFF = 32,767
Microprocessors80x86 Family Overview43
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Jump InstructionJMP target ⇒ JMP near target (assembler chooses near or short)JMP FAR
JMP 1024 IP ←16 1024
JMP NEAR [1024] IP ←16 [1024] JMP target
JMP NEAR [SI] IP ←16 [DS:SI]
JMP FAR 1122:3344 CS ←16 1122 IP ←16 3344
JMP FAR [1024] CS ←16 [1026] IP ←16 [1024]
JMP far target
JMP FAR [SI] CS ←16 [DS:SI+2] IP ←16 [DS:SI]
Microprocessors80x86 Family Overview44
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Call and Return
CALL near target PUSH IP
IP ← target
CALL 1024 PUSH IP
IP ← 1024
CALL [SI] PUSH IP
IP ← [DS:SI]
RET POP IP
CALL far target PUSH CS PUSH IP
CS ← SEG
IP ← OFF
CALL 1122:3344 PUSH CS PUSH IP
CS ← 1122
IP ← 3344
CALL [SI] PUSH CS PUSH IP
CS ← [DS:SI+2]
IP ← [DS:SI]
RETF POP IP POP CS
Microprocessors80x86 Family Overview45
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Indirect Far Call
stackSP
CS
IP fall-throughCALL [SI]
DS
SI
44332211
stack
SP
CS = 4433
IP = 2211
fall-throughCALL [SI]
DS
SI
44332211
fall-through CSfall-through IP
Microprocessors80x86 Family Overview46
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Interrupt Vector TableTransfers control to Interrupt Service Routine (ISR)
ISR can be stored anywhere in memory
Interrupt Vector Table Table Starts at physical address 00000Vector = 4 bytes = CS (2 bytes) + IP (2 bytes)
Vector 0 at physical address 00000Vector 1 at physical address 00004Vector 2 at physical address 00008
ISR vector addressFor interrupt N
IP (L)N × 4 + 0
IP (H)N × 4 + 1
CS (L)N × 4 + 2
CS (h)N × 4 + 3
Microprocessors80x86 Family Overview47
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Software Interrupt Instructions
INT type INT 21H PUSH flags IF ← 0 TF ← 0 PUSH CS PUSH IP CS ← [00087H.00086H]IP ← [00085H.00084H]
IRET none IRET POP IP POP CS POP flags
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Interrupt
stackSP
CS
IP fall-throughINT 21
00000
00084
44332211
stack
SP
fall-throughINT 21
00000
00084
44332211
flagsfall-through CSfall-through IP
CS = 4433
IP = 2211
Microprocessors80x86 Family Overview49
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Processor Control Instructions
STC CF ← I Set carry flag
CLC CF ← 0 Clear carry flag
CMC CF ← not(CF) Complement carry flag
STD DF ← 1 Set direction flag
CLD DF ← 0 Clear direction flag
STI IF ← I Set interrupt flag
CLI IF ← 0 Clear interrupt flag
HLT None CPU stops — requires reset
WAIT None Enter wait state
NOP None No operation
Microprocessors80x86 Family Overview50
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LEA
Load Effective AddressSimilar to MOVCopies address (pointer) of memory locationDoes not access memory
←⎯⎯⎯⎯
←⎯⎯⎯⎯
←⎯⎯⎯⎯
←⎯⎯⎯⎯
←⎯⎯⎯⎯
16-bits
16-bits
16-bits
16-bits
16-bits
dest, [EA] dest EA
BX, [x] BX &(x)
AX, [1234] AX 1234
CX, [SI+12] CX SI+12
DX, [BX
LEA
LEA
LEA
+D
LEA
LE I] DX A BX +DI
Microprocessors80x86 Family Overview51
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Moving Data Around
MOV SI,1122 ; SI ← 1122
MOV [0000],SI ; [DS:0000] ← 1122
MOV BX,3344 ; BX ← 3344
MOV [BX],SI ; [DS:3344] ← 1122
MOV [BX+SI],BX ; [DS:4466] ← 3344
LEA BX,[BX+SI] ; BX ← 4466
MOV CS,[BX] ; CS ← [DS:4466]
MOV AX,[BX+2] ; AX ← [DS:4468]
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LDS and LESLoads 32-bit logical address of type DS:EA
←⎯⎯⎯⎯
←⎯⎯⎯⎯
←⎯⎯⎯⎯
←⎯⎯⎯⎯
←⎯⎯⎯⎯
←⎯⎯⎯⎯
16-bits
16-bits
16-bits
16-bits
16-bits
16-bits
LDS dest, [EA] dest [EA]
DS [EA +2]
LDS BX, [SI] BX [DS:SI]
DS [DS:SI+2]
LES dest, [EA] dest [EA]
ES [EA +2]
11 22 33 44
DS ← 3344
55 DS:SI → 66
BX ← 5566
77 88 99 AA
DS
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Switching Data Tables/* DO ARITHMETIC WITH DS:BX = 1111:2222 *//* SWITCH DATA TABLES */
MOV [SI], 4444 ; [SI] ← 4444MOV [SI+2], 3333 ; [SI+2] ← 3333PUSH DS ; SP ← SP – 2
; [SS:SP] ← 1111PUSH BX ; SP ← SP – 2
; [SS:SP] ← 2222LDS BX,[SI] ; BX ← 4444
; DS ← 3333/* DO ARITHMETIC WITH DS:BX = 3333:4444 *//* SWITCH BACK TO FIRST DATA TABLE */
POP [SI] ; [SI] ← 2222; SP ← SP + 2
POP [SI+2] ; [SI+2] ← 1111; SP ← SP + 2
LDS BX,[SI] ; BX ← 2222; DS ← 1111
Microprocessors80x86 Family Overview54
Dr. Martin LandHadassah CollegeSpring 2011
Data Movement ⎯ I/O Operations ⎯ 180x86 processors control an I/O signal on the memory bus
I/O signal is off to select processor access to RAMI/O signal is on to select processor access to I/O busMOV selects RAM accessIN and OUT select I/O access
AL or AX are always src/dest for I/O instructionsI/O address is called a port
can range from 0000 H to FFFF H
direct mode ⎯ 1 immediate byte addressindirect mode ⎯ 2 address bytes in DX
Microprocessors80x86 Family Overview55
Dr. Martin LandHadassah CollegeSpring 2011
Data Movement ⎯ I/O Operations ⎯ 2
זיכרון מטמון
cache memory
ה חישוביהידתהמ ר כזי
Central Processing Unit (CPU)
זיכרון ר א שי
Main Memory(RAM)
מת אם א פי ק Bus
Adapter
Memory Busא פי ק זיכ ר ון
I/O Busפ לט / א פי ק קלט
פ לט / בקר קלט I/O Controller
פ לט / בקר קלט I/O Controller
פ לט / בקר קלט I/O Controller
Disk ממשק משתמש
רשת תקש ורת communications
network
Microprocessors80x86 Family Overview56
Dr. Martin LandHadassah CollegeSpring 2011
Data Movement ⎯ I/O Instructions ⎯ 3
IN AL,26H AL ← port 26H
IN AX,26H AL ← port 26H; AH ← port 27H
input byte from port 0 ⎯ 255
IN AL,DX AL ← port DX IN acc, port
IN AX,DX AL ← port DX AH ← port DX+1
input byte from port 0 ⎯ 65,535 (address in DX)
OUT port, acc OUT DX,AX port DX ← AL port DX+1 ← AH
output byte to port 0 ⎯ 65,535 (address in DX)