Post on 04-Jun-2018
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Pipeline Hazards
(Second Edition: Sections 6.4-6.6Fourth Edition: Sections 4.7, 4.8from Dr. Andrea Di Blas’ notes
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CMPE 110 – Spring 2011 – J. Ferguson
Outline• Structural hazards: lack of resources
• Data hazards: data dependencies betweeninstructions
• Control hazards: branches
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CMPE 110 – Spring 2011 – J. Ferguson
Hazards
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Hazards are situations that prevent the nextinstruction from moving through the pipeline
• Structural Hazards are caused by conflicts inresource usage.
• Data Hazards are caused by instructions thatrequire results from a previous (uncompleted)instruction.
• Control Hazards are caused by instructions thatchange the Program Counter.
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CMPE 110 – Spring 2011 – J. Ferguson
Structural Hazards• Overlapping instructions requires the
duplication of resources so that not all
instruction combinations are possible.• The pipeline is said to have a structural
hazard if some combinations ofinstructions can not be accommodated.
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When a structural hazard occurs the pipeline is stalled. The
latter of the stages requiring the resource does not advancewhile the resource is used by the earlier instruction.
bubble
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CMPE 110 – Spring 2011 – J. Ferguson
Stalls represented by a
“bubble” in the pipeline
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CMPE 110 – Spring 2011 – J. Ferguson
Data Hazards• Data hazards occur when an instruction reads data
before it is written by a previous instruction.
• Examplesadd $8, $7, $6 sub $9, $8, $5 -----------------
lw $7, 16($5) ori $8, $4, $7
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The next 2 instructions after the sub will getthe “old” value in $2 (assuming that written datainto registers will be read in same cycle).
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CMPE 110 – Spring 2011 – J. Ferguson
Forwarding or Bypassing
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CMPE 110 – Spring 2011 – J. Ferguson
Actual Forwarding
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CMPE 110 – Spring 2011 – J. Ferguson
Forwarding on DataPath
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CMPE 110 – Spring 2011 – J. Ferguson
More Detail (Forwarding Unit)
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CMPE 110 – Spring 2011 – J. Ferguson
Forwarding Unit logic
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If((EX/MEM.Rdest = ID/EX.Rs) && EX/MEM.WB)Forward EX/MEM.ALUresult to Rs input of ALU
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CMPE 110 – Spring 2011 – J. Ferguson
Why not always forward from
EX/MEM buffer?
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CMPE 110 – Spring 2011 – J. Ferguson
Summary of “forwarded” hazards
• “ALU to ALU” hazards:
• Ifadd $3, $4, $8 add $6, $3, $8 Take register value from the EX/MEM pipeline register
• Ifadd $3, $4, $8 a “non-dependent” instruction add $6, $3, $8
Take register value from the MEM/WB pipeline register
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CMPE 110 – Spring 2011 – J. Ferguson
Store instruction data
dependency
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New register value become available cc4, not cc3
Forwarding doesn’t work for this instruction!
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CMPE 110 – Spring 2011 – J. Ferguson
Load instruction data dependency
must stall…
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… and be forwarded!
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CMPE 110 – Spring 2011 – J. Ferguson
What happens “in” the Bubble?
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CMPE 110 – Spring 2011 – J. Ferguson
Hazard Detection Unit (or Pipeline Interlock)
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The HDU checks if EX instruction is a load and the EXinstruction destination register is source register in the IDinstruction. If so, it stalls the IF and ID stages for onecycle.
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CMPE 110 – Spring 2011 – J. Ferguson
Load Data Hazards adds a ClockCycle to the Pipeline
• How much does this slow down the computer?– One extra clock cycle for each instruction
–
Is that a lot?• Software solution: Whenever possible, reorderinstructions so that the next instruction is notdependent on the destination of the Loadinstruction.
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CMPE 110 – Spring 2011 – J. Ferguson
Example: InstructionReordering
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Loop addi $5, $5, 4
lw $8, 0($5)add $7, $8, $9sw $7, 0($4)addi $4, $4, 4
bne $4, $10, Loop
Loop addi $5, $5, 4
lw $8, 0($5)addi $4, $4, 4add $7, $8, $9sw $7, -4($4)
bne $4, $10, Loop
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CMPE 110 – Spring 2011 – J. Ferguson
Control Hazards
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Control instructions may change the flow of thenext instruction to be executed. We have thatevaluation in the EX stage.
Simple solution is to stall the pipeline until branch resolved
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CMPE 110 – Spring 2011 – J. Ferguson
Partial Solution:
Resolve Branch Sooner
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CMPE 110 – Spring 2011 – J. Ferguson
From 3 to 1 stage bubble
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Must “flush” IF to get rid of bubble.
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CMPE 110 – Spring 2011 – J. Ferguson
Second Improvement:Speculative Execution
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Start on next instruction, flush only if needed
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CMPE 110 – Spring 2011 – J. Ferguson
MIPS approach: Delayed Branch
• Always execute the next instruction after thebranch.
• Compiler reorders instructions to put useful
instruction after the branch (one that must beexecuted anyway).
• If no useful instruction: put NOP after thebranch.
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CMPE 110 – Spring 2011 – J. Ferguson
Example of Delayed Branch
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Loop addi $5, $5, 4
lw $8, 0($5)addi $4, $4, 4add $7, $8, $9sw $7, -4($4)bne $4, $10, Loop….
Loop addi $5, $5, 4
lw $8, 0($5)addi $4, $4, 4add $7, $8, $9 bne $4, $10, Loopsw $7, -4($4)….
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CMPE 110 – Spring 2011 – J. Ferguson
Check our understanding
•
Allowing jumps, branches and ALU instructions totake fewer stages (and cycles) will increaseperformance under all circumstances.
• Allowing some instructions to take fewer cyclesdoes not help, because only one instruction will be
executed per clock cycle.• Instead of trying to take fewer cycles, perhaps we
can explore making the pipeline longer by thecycles shorter.
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Observation: not all instructions need allfive cycles of the pipeline. Which are correctif you ignore all hazards?